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Table 2-3. Receive Statistics Vector Descriptions
Functional Description
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15:0
Description
Long Frame . This bit is set when a frame longer than specified in the MAX_PKT_SIZE register is received.
Short Frame . This bit is set when a frame shorter than 64 bytes is received.
IPG Violation . This bit is set when a frame is received before the IPG timer runs out (96 bit times).
Not Used . This bit always returns a zero.
Carrier Event Previously Seen . When asserted, indicates that a carrier event was detected since the last
frame.
Packet Ignored . When set, this bit indicates the incoming packet is to be ignored.
CRC Error . This bit is set when a frame is received with an error in the CRC field.
Length Check Error . This bit is set if the number of data bytes in the incoming frame do not match the value in
the length field of the frame.
Receive OK . This bit is set if the frame is received without any error.
Multicast Address . This bit is set to indicate the received frame contains a Multicast Address.
Broadcast Address . This bit is set to indicate the received frame contains a Broadcast Address.
Dribble Nibble . This bit is set when only four bits of the data presented on the RS interface are valid.
Unsupported Opcode . This bit is set if the received control frame has an unsupported opcode. In this version of
the IP, only the opcode for PAUSE frame is supported.
Control Frame . This bit is set to indicate that a Control frame was received.
PAUSE Frame . This bit is set when the received Control frame contains a valid PAUSE opcode.
VLAN Tag Detected . This bit is set when the TSMAC IP core receives a VLAN Tagged frame.
Frame Byte Count . This bus contains the length of the frame that was received. The frame length includes the
DA, SA, L/T, TAG, DATA, PAD and FCS fields.
Transmit MAC (Tx MAC)
The Tx MAC is responsible for controlling access to the physical medium. The Tx MAC reads data from an external
Tx FIFO when the FIFO is not empty and it detects an active tx_fifoavail. The Tx MAC then formats this data into an
Ethernet packet and passes it to the G/MII module.
The Tx MAC is disabled while Tx_en is low (Bit_3 of the MODE register) and should only be enabled after the asso-
ciated registers are properly initialized. Once enabled, the Tx MAC will continuously monitor the FIFO interface for
an indication that frame(s) are ready to be transmitted. In the 1G mode, Tx MAC and the Tx FIFO interface opera-
tions are synchronous to txmac_clk derived from sys_clk. In the 10/100 mode, the Tx MAC is clocked by txmac_clk
(derived from the tx_clk supplied from the PHY device). The Tx FIFO interface signals are always synchronous to
txmac_clk.
In 10/100 mode, the Tx MAC can be configured to operate in the half-duplex or full-duplex mode. This is done by
writing to bit[5] of the TX_RX_CTL register. In full-duplex operation, it is possible for the receiver’s buffer to fill up
rapidly. In such cases, the receiver sends flow control (PAUSE) frames to the transmitter, requesting that it stop
transmitting frames. When the receiver is able to free the buffers, the transmitter completes transmitting the current
frame and stops for the duration specified in the PAUSE frame.
Transmitting Frames
By default, the Transmit MAC is configured to generate the FCS pattern for the frame to be transmitted. However,
this can be prevented by setting bit[2] of the Tx_RX_CTL register. This feature is useful if the frames being pre-
sented for transmission already contain the FCS field. When FCS field generation by the MAC is disabled, it is the
user’s responsibility to ensure that short frames are properly padded before the FCS is generated. If the MAC
receives a frame shorter than 64 bytes when FCS generation is disabled, the frame is sent as is and a statistic vec-
tor for the condition is generated.
IPUG51_03.0, December 2010
22
Tri-Speed Ethernet MAC User’s Guide
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